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Test Synthesis Using Encounter RTL Compiler

"As FPGAs perform more functions within systems, there is an increasing level of interest among our customers for technologies that help reduce development times," said Chris Balough, senior director of software, embedded, and DSP marketing at Altera. "Cadence's C-to-Silicon Compiler provides an innovative approach to high-level synthesis that helps FPGA designers increase their productivity and quality of results."

The following Cadence CAD tools will be used in this lab: RTL Compiler Ultra for logic synthesis
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The C-to-Silicon Compiler was launched in July 2008 with two unique capabilities in high-level synthesis, Embedded Logic Synthesis (ELS) and a Behavior Structure Timing (BST) database. ELS uses Cadence Encounter RTL Compiler global synthesis to help ensure high accuracy and high-quality implementation results. The BST database enables design teams to perform true incremental synthesis-for example, re-synthesizing only the parts of the design that changed while leaving the rest of the design untouched. The latest release of the C-to-Silicon Compiler extends these capabilities from ASICs to FPGAs, with the same benefits.

Cadence's RTL Compiler wins synthesis poll | EE Times

RTL Compiler from Cadence Design Systems Inc
Photo provided by Flickr

Before you proceed to Place and Route you will no doubt want to perform a simulation in Cadence of the gate level verilog code that you just synthesized. The import tool for icfb is found under File->Import->Verilog.

The Cadence C-to-Silicon Compiler is available in limited production, and is designed to work with the Altera's Quartus II software and Xilinx Synthesis Technology FPGA-synthesis tools available from Altera and Xilinx, respectively.

Cadence Encounter RTL Compiler | Sudip Shekhar

Cadence RTL Compiler Synthesis …
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It combinesRTL synthesis, silicon virtual prototyping, automated floorplansynthesis, clock network synthesis, design for manufacturability andyield, low-power and mixed-signal design support, and nanometerrouting.

Theflow includes power optimization through clock-gating insertion, aswell as proven prevention of signal-integrity problems through analysisand repair.

The reference flow incorporates the following Cadence tools:

The Cadence SoC Encounter System
Encounter RTL Compiler global synthesis
CeltIC NDC
CadenceNanoRoute router
VoltageStorm power grid verification
Encounter Conformal verification technologies
Cadence QRC Extraction
Assura DRC/LVS physical verification.

has adopted the Cadence® Encounter® RTL Compiler for synthesis, ..
Photo provided by Flickr
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RTL Synthesis and Test - Synopsys

"We are starting to use C-to-Silicon Compiler in several production ASIC designs, and are recommending it to the other Hitachi design groups," said Toru Hiyama, general manager, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi, Ltd. "We requested Cadence for FPGA synthesis support earlier last year, expecting more designers would use C-to-Silicon Compiler not only for ASIC designs but also for high-priority FPGA designs. We are very pleased to see FPGA support capability available on C-to-Silicon Compiler, and the quality of results using C-to-Silicon Compiler is very promising."

rtl compiler based synthesis flow - 1 Getting Started …

Cadence Design Systems, a specialist in global electronic design, has announced the integration of FPGA-synthesis for Altera and Xilinx FPGAs with the Cadence C-to-Silicon Compiler, its flagship electronic system-level (ESL) technology for hardware design and implementation. C-to-Silicon Compiler, recently selected as one of EDN's "Hot 100 Electronic Products of 2008," improves designer productivity up to 10 times in creating and re-using system-on-chip IP. Originally focused on ASICs, this new version of C-to-Silicon Compiler delivers the same productivity benefits to designers of system-on-chip IP blocks targeting Altera and Xilinx FPGAs.

RTL Compiler is an HDL synthesis …

A digital design is described by an HDL language such as VHDL or Verilog. Shown below in Figure 3 is a 4-bit counter written in RTL VHDL. This design will be used as the example in this tutorial.

Encounter RTL Compiler global synthesis CeltIC NDC

"The C-to-Silicon Compiler very effectively handles mixed control/datapath designs, as well as incremental synthesis," said Steve Svoboda, product marketing director at Cadence. "In response to several customer requests this year, we applied our unique ELS technology to designs targeting the Altera and Xilinx FPGA families like we did with Cadence RTL Compiler. As a result, customers now get the same advantages with high-level synthesis whether they are targeting their designs to FPGAs or to ASICs."

Estimating power consumption in cadence RTL compiler with VCD file

Table 1 shows which tools were used for the Jazz SBC18HA process. Note that RTL was done in VHDL but the output of the synthesis was in Verilog in order to be compatible with the Jazz libraries for this process. The RTL may be written in Verilog if the designer is more comfortable with it.

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